\doxysubsubsubsection{RCCEx I2\+C2 Clock Source }
\hypertarget{group___r_c_c_ex___i2_c2___clock___source}{}\label{group___r_c_c_ex___i2_c2___clock___source}\index{RCCEx I2C2 Clock Source@{RCCEx I2C2 Clock Source}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
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\Hypertarget{group___r_c_c_ex___i2_c2___clock___source_ga4c1d277a9e8826e43ec7b6b62565930d}\label{group___r_c_c_ex___i2_c2___clock___source_ga4c1d277a9e8826e43ec7b6b62565930d} 
\#define {\bfseries RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+D2\+PCLK1}~RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+D2\+PCLK1
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\Hypertarget{group___r_c_c_ex___i2_c2___clock___source_ga4c8879f57583423efce93b5420213d15}\label{group___r_c_c_ex___i2_c2___clock___source_ga4c8879f57583423efce93b5420213d15} 
\#define {\bfseries RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+PLL3}~RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+PLL3
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\Hypertarget{group___r_c_c_ex___i2_c2___clock___source_gab2d1849bb1ec2df29cab79843441e3cc}\label{group___r_c_c_ex___i2_c2___clock___source_gab2d1849bb1ec2df29cab79843441e3cc} 
\#define {\bfseries RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+HSI}~RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+HSI
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\Hypertarget{group___r_c_c_ex___i2_c2___clock___source_ga34323d683125806be2a0df9125fccb0e}\label{group___r_c_c_ex___i2_c2___clock___source_ga34323d683125806be2a0df9125fccb0e} 
\#define {\bfseries RCC\+\_\+\+I2\+C2\+CLKSOURCE\+\_\+\+CSI}~RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+CSI
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\doxysubsubsubsubsection{Detailed Description}
